IC's are prone to damage from electrostatic discharge (ESD). This is especially true for metal-oxide semiconductor (MOS) type IC's whose field-effect transistors (FET's) utilize thin gate dielectrics that rupture at moderate voltages. For example, conventional MOS-type gate dielectrics employ about 500-1,000 angstroms of silicon dioxide which ruptures at 6-9 volts/100 angstroms. Thus, 30 volts across a 500-angstrom oxide dielectric could destroy it.
In addition to oxide rupture, ESD currents on the order of an ampere often appear at the IC terminals. If the heat generated by these currents is not properly dissipated, electromigration of the metal in the lead pattern and microdiffusion of dopants in the IC can occur. The result is a short between the IC's substrate region and the lead pattern.
Generally, an MOS-type IC is most susceptible to ESD damage during assembly, test, transfer, and installation when a voltage generated by a person handling the IC discharges across it. A person can easily develop 1,000-10,000 volts. The destructive effect of this high voltage is partially alleviated by the source resistance of the human body. However, the resulting ESD signal can still be very damaging. To prevent dielectric rupture, a protection device for dissipating ESD energy is conventionally connected between each input terminal of an MOS IC and its operative section.
In evaluating such an input protection device, a circuit representing the human body is conventionally employed. FIG. 1 illustrates how such a "human body" circuit interacts with an IC 10 having an input terminal 12 that receives the resulting ESD input signal V.sub.I from the human body. In this circuit, a source voltage V.sub.S representing the actual ESD voltage is applied through a two-pole switch 14 to a grounded capacitor C.sub.S representing the human body capacitance of about 100-200 picofarads. After capacitor C.sub.S is charged to V.sub.S, switch 14 is moved from its charging position to its discharging position. Capacitor C.sub.S then discharges through a resistor R.sub.S representing the human body resistance of 1,000-2,000 ohms so as to generate signal V.sub.I.
Terminal 12 is connected to an input protection device 16 which operates on signal V.sub.I to produce a modified input signal V.sub.C that is desirably not strong enough to damage a protected gate 18 of IC 10 to which signal V.sub.C is supplied. Insofar as device 16 protects gate 18, resistor R.sub.S is part of the operational dynamics since it modulates the V.sub.S discharge from capacitor C.sub.S.
Numerous types of devices have been considered for IC input protection. J. Keller, "Protection of MOS Integrated Circuits from Destruction by Electrostatic Discharge," Proceedings of the 1980 Electrical Overstress/Electrostatic Discharge Symposium, pp. 73-80, provides a good summary of various MOS input protection circuits.
FIG. 2 illustrates one of the prior art input protection schemes discussed by Keller for IC 10 when it is an N-channel IC fabricated on a semiconductor substrate having a P-type substrate region which receives a reference voltage V.sub.SS. In this protection device 16, an N-type diffused resistor RA connected between terminal 12 and gate 18 limits the current flow. Resistor RA does not have a high value, however, because it would unacceptably attenuate signal V.sub.C. Even a moderate RA value such as 1,000 ohms which is conventional may unduly attenuate the V.sub.C voltage.
The P-type substrate region forms a PN diode JA with the N-type material of resistor RA. Diode JA is normally reverse biased. Its reverse breakdown voltage V.sub.B D is less than the rupture voltage V.sub.R of the thin-oxide gate dielectrics in IC 10. Assuming that V.sub.SS is ground, diode JA breaks down by avalanching to provide a path for transmitting the V.sub.I current to the V.sub.SS supply when the V.sub.I voltage reaches V.sub.BD. This is intended to prevent the V.sub.I voltage from rising to V.sub.R. However, due to the time needed for breakdown to occur, the V.sub.I voltage may still pass V.sub.BD and reach V.sub.R to damage gate 18. Diode JA is typically useful for V.sub.S values up to several hundred volts above which it permanently breaks down. When the V.sub.I voltage drops slightly below ground, diode JA turns on to provide (positive) current from the V.sub.SS supply. This prevents voltage V.sub.I from dropping to -V.sub.BD and likewise protects gate 18.
An N-channel enhancement-mode thin-oxide insulated-gate FET QA is conventionally employed with elements RA and JA. FET QA is a punch-through FET whose drain is connected between resistor RA and gate 18 and whose insulated gate is connected through a parasitic resistance RB to the QA source which, in turn, is connected to the V.sub.SS supply through a parasitic resistance RC. Because they are the inherent resistances of the electrical connections for the QA gate and source, resistances RB and RC are small, typically no more than 25-50 ohms each. When the V.sub.I voltage is positive, FET QA protects gate 18 principally by punch-through as the depletion region of the QA drain extends to the QA source to provide a conductive path to the V.sub.SS supply. FET QA also lowers the breakdown voltage of the portion of diode JA near the QA drain. Where the gate dielectrics in IC 10 are about 1,000 angstroms, human body resistor R.sub.S is about 1,500 ohms, and human body capacitor C.sub.S is about 100 picofarads, the combination of FET QA and resistor/diode RA and JA prevents V.sub.S values up to about 1,500 volts from damaging gate 18.
FIG. 3 illustrates another example of device 16 described by Keller for IC 10 when it is an N-channel IC. In FIG. 3, device 16 again contains diffused resistor/diode RA and JA connected and operable as before. A PN diode JB whose anode is the P-type substrate region at V.sub.SS and whose cathode is connected to terminal 12 functions in the manner described for diode JA.
The important addition to device 16 in FIG. 3 is an N-channel (enhancement-mode) thick-oxide insulated-gate FET QB whose drain is connected to gate 18. The QB source receives voltage V.sub.SS while the QB insulated gate is connected to terminal 12. The gate dielectric of FET QB consists of part of a silicon-dioxide field region that laterally individually surrounds active semiconductor regions containing electronic components of IC 10. This field-oxide gate dielectric is of such a thickness that the threshold voltage V.sub.T of FET QB is less than V.sub.R but greater than the V.sub.I levels reached during normal IC operation. Should the V.sub.I voltage rise above the V.sub.T of FET QB, it turns on so as to provide a path to the V.sub.SS supply to inhibit the V.sub.I voltage from rising further. Should the V.sub.I voltage attempt to rise even further, FET QB acts as a punch-through FET in which its drain depletion region extends to its source so as to provide a wider current path to the V.sub.SS supply. For the conditions given above for FIG. 2, input protection devices employing thick-oxide FET's such as FET QB can prevent damage at V.sub.S values up to 2,500-3,000 volts.
Under more stringent conditions where, for example, the gate dielectric thickness is 500 angstroms, R.sub.S is 1,000 ohms, and C.sub.S is 200 picofarads, the above devices do not perform as well. It does not appear that they would provide protection at V.sub.S values of 1,500 volts or more. Moreover, most of the ESD energy is dissipated at the front end of resistor RA connected to terminal 12 because FET QA or QB is connected to the back end of resistor RA. This can lead to metal electromigration and dopant microdiffusion near the front end of resistor RA.